1. Field of the Invention
The present invention relates to a hardware engine control apparatus that controls a plurality of hardware engines (HWEs) that execute a series of plurality of different kinds of processing with different control timings.
2. Description of the Related Art
In recent years, a large number of standards concerning signal processing such as moving image processing and radio communication processing are specified. In these standards, data size, processing speed, and the like are specified as parameters. Therefore, a system that performs the signal processing needs to flexibly cope with changes in the parameters.
On the other hand, according to improvement of performance and a reduction in prices of apparatuses for the signal processing, it is also demanded to realize a plurality of standards with one system LSI. For example, there is a demand for a system LSI in which a plurality of standards are integrated such as a moving image processing LSI in which H.264, which is the standard of moving image compression of the ITU-T, and MPEG, which is the standard of moving image compression and expansion of the ISO, are integrated and a radio communication LSI in which a wireless LAN by the standard of the IEEE and ISDB-T, which is the standard of the terrestrial digital broadcast in Japan, are integrated.
In the development of such LSIs, to realize a reduction in a design period and a reduction in cost, it is desirable to extract common arithmetic processing out of processing of the integrated standards and share the extracted arithmetic processing as a hardware engine (hereinafter, “HWE”). However, even if the arithmetic processing is shared, data size treated in the arithmetic processing, required arithmetic processing speed, and the like are different among the standards. Therefore, control corresponding to each of the standards has to be applied to the HWE. Consequently, in realizing a plurality of standards with one system LSI, it is necessary to realize a flexible HWE control mechanism that can absorb parameter changes in the standards and differences among the standards. To realize the flexible HWE control mechanism, it is important to improve a degree of freedom of a control range and make it possible to finely control the HWE at a clock cycle.
In Japanese Patent Application Laid-Open No. 08-101805, a data bus, an arithmetic unit (ALU), a multiplier (MPY), and an accumulating adder (ACC) configure a processor. Data memories are interposed between the data bus and a plurality of dedicated HWEs (DCTs that perform discrete cosine transform and filter circuits (FLT) that perform arithmetic processing for image data). Data transfer between the processor and the dedicated HWEs is realized through the data memories. An amount of access to the data bus during the data transfer to the HWEs is reduced by connecting the data memories and the HWEs by a dedicated bus. Control for start, stop, and the like of the HWEs is realized by mapping the HWEs to a memory address space of the processor.
In Japanese Patent Application Laid-Open No. 08-101805, the HWEs are controlled through the memory address space. Therefore, there is an advantage that flexible control can be performed by rewriting software. On the other hand, for example, fine real-time control in block cycle units cannot be performed and the HWEs cannot be simultaneously controlled.